RISC-V is coming!

RISC-V Website

RISC-V is coming and it is coming faster to market than you may think. The prospect for semiconductor manufacturers to be able to do ASIC designs without the additional cost of ARM IP is accelerating RISC-V to market sooner rather than later. Also, if RISC-V gets their security model right, it may potentially dominate the market for that reason alone. If you are a professional in the embedded industry, you better be prepared for it!

Many may not realize it, but the various sub systems of your average SoC implement maybe 10-15 different ISA of varying IP cost and complexity. For those developing SoC designs it is a mess of different toolchains involved. RISC-V seeks to simplify this situation by offering a free, open and scalable ISA that spans from the simplest 32-bit microcontroller cores to 64-bit microprocessor cores with various extentions, including custom extensions. Actually, even a 128-bit ISA is being drafted so the future looks bright.

Naturally, ARM and RISC-V, are very alike because they are both RISC architectures. According to researchers, RISC-V should be able to achieve similar or even better performance and power savings than ARM.

Industry is learning from the success of the open source movement and so it makes perfect sense for the industry to colaborate and create a free open ISA for everyone to use. It will bring lower cost, spur new innovations, and improve the way we work.


If you take a closer look at the documenation for any given RISC-V CPU implementaton you may notice a magic code meant to classify the specific CPU implmenetation. For example, the GD32VF103 chip from Gigadevice is described as a “RV32IMAC”. This magic code translates into the CPU implementing the following features:

Key   Feature
RV32   RISC-V 32-bit little endian
I   Base integer with 32 32-bit general purpose registers
M   Integer multiplication and division
A   Atomic operations
C   Compressed instructions

Below you can find an overview of all the codes that are available to classify a given RISV-C CPU implementation:

RISC-V ISA Overview

Notice that IMACFDQ are all part of the socalled “Base ISA” which is already ratified/frozen. Also notice that there are two specifications to describe the RISC-V ISA: “The User ISA Specification” and “Privileged ISA Specification”, both of which have been ratified at this point.


If you need to configure a toolchain for RISC-V you will also need to know the magic code which specify the ABI. For example, for the GD32VF103 CPU, the ABI is described by the code “ilp32”. This means that the ABI data model is represented by integers, long integers, and pointers, each 32-bit in size. The ABI code also specifies which floating point model is used. For example, “ilp32f” means added single precision (32-bit) floating point support.

For more information on available ABI codes for RISC-V see here.

RISC-V ISA Documentation

We can’t have a blog post introducing the RISC-V ISA without also including links to the ISA documentation. So here we go:

The RISC-V Instruction Set Manual - Volume I: Unprivileged ISA

The RISC-V Instruction Set Manual - Volume II: Privileged Architecture